1. Field of the Invention
The present invention relates to a semiconductor device and an information processing system including the same. More particularly, the present invention relates to a semiconductor device that includes plural core chips and an interface chip to control the cores and an information processing system including the same.
2. Description of the Related Art
A memory capacity that is required in a semiconductor memory device such as a dynamic random access memory (DRAM) has increased every year. In recent years, a memory device that is called a multi-chip package where plural memory chips are laminated is suggested to satisfy the required memory capacity. However, since the memory chip used in the multi-chip package is a common memory chip capable of operating even though the memory chip is a single chip, a so-called front end unit that performs a function of an interface with an external device (for example, memory controller) is included in each memory chip. For this reason, an area for a memory core in each memory chip is restricted to an area obtained by subtracting the area for the front end unit from a total chip area, and it is difficult to greatly increase a memory capacity for each chip (for each memory chip).
In addition, a circuit that constitutes the front end unit is manufactured at the same time as a back end unit including a memory core, regardless of the circuit being a circuit of a logic system. Therefore there have been a further problem that it is difficult to speed up the front end unit.
As a method to resolve the above problem, a method that integrates the front end unit and the back end unit in individual chips and laminates these chips, thereby constituting one semiconductor memory device, is suggested (for example, Japanese Patent Application Laid-Open (JP-A) No. 2007-157266). According to this method, with respect to plural core chips each of which is integrated with the back end unit without the front end unit, it becomes possible to increase a memory capacity for each chip (for each core chip) because an occupied area assignable for the memory core increases. Meanwhile, with respect to an interface chip that is integrated with the front end unit and is common to the plural core chips, it becomes possible to form its circuit with a high-speed transistor because the interface chip can be manufactured using a process different from that of the memory core. In addition, since the plural core chips can be allocated to one interface chip, it becomes possible to provide a semiconductor memory device that has a large memory capacity and a high operation speed as a whole.
However, this kind of semiconductor memory device is recognized as only one memory chip, in view of a controller. For this reason, when the plural core chips are allocated to one interface chip, how to perform an individual access to each core chip becomes a problem. In the case of the general multi-chip package, each memory chip is individually selected using a dedicated chip selection terminal (/CS) in each memory chip. Meanwhile, in the semiconductor memory device described above, since the chip selection terminal is provided in only the interface chip, each core chip cannot be individually selected by a chip selection signal.
In order to resolve this problem, JP-A No. 2007-157266 described above, a chip identification number is allocated to each core chip, a chip selection address is commonly provided from the interface chip to each core chip, and individual selection of each core chip is realized.
However, since the chip selection address that is described in JP-A No. 2007-157266 is not used in the common semiconductor memory device, compatibility with the semiconductor memory device according to the related art may be lost.
As a result of examinations made by the present inventor from the above viewpoint, the inventor has found that compatibility with conventional semiconductor memory devices can be maintained by using a part of address information for a chip selection signal. According to this configuration, it appears from a controller that an address space is simply enlarged. Therefore, an interface that is same as that for the conventional semiconductor memory devices can be used.
However, in a semiconductor memory device such as a DRAM, there is employed a system of performing a read operation or a write operation by performing a row access and a column access in this order. Therefore, a part of address information used as a chip selection signal is supplied at only one of timings of a row access and a column access. Accordingly, when a chip selection signal is supplied at a row access time, for example, a chip selection signal is not supplied at a column access time. Consequently, it is not possible to determine which one of core chips is selected at the column access time.
This problem of accessing does not occur when each core chip is divided into plural memory banks and also when each memory bank is configured across plural core chips as viewed from a memory controller. This is because a bank address signal for assigning a memory bank is supplied at both timings of the row access time and the column access time. That is, when chip activation information is held in a predetermined core chip when a predetermined memory bank in this predetermined core chip is selected at a row access time, a column access to the predetermined memory bank in the predetermined core chip can be performed even when a chip selection signal is not supplied at the column access time.
However, in a semiconductor memory device having plural memory banks, two or more memory banks can operate in parallel. Therefore, pieces of chip activation information can be simultaneously in an active state in plural core chips. Even in this case, an access failure does not occur because a bank address signal is supplied at the column access time. That is, in a core chip in which the chip activation information is in an active state, a column access is received regardless of the bank address signal. However, because a column access to a memory bank that is not in an active state becomes invalid, damaging of data or conflict of data does not occur.
However, because an invalid column access increases its power consumption, it is preferable to reduce power consumption by preventing such a column access. The above problem applies not only to a so-called semiconductor memory device such as a DRAM but also to a semiconductor device in general that includes a memory in a part thereof.